A subsampling time-domain digital filter responds to a digital signal supplied at a relatively high sample rate to generate a digital output signal at a relatively low sample rate. Input digital signal samples are grouped into sets of samples contiguous in time, each set of samples then being weighted and summed together to generate a respective output signal sample. If all weights are positive-valued, the subsampling filter will exhibit a low-pass filter response. A subsampling filter exhibiting a low-pass filter response is sometimes referred to as a "decimation" filter, especially when such a filter is used together with an oversampling analog-to-digital converter.
In a subsampling time-domain digital filter, rather than differentially delaying the input signal samples in each set and parallelly adding them after weighting, thereby to generate output signal samples, an accumulator can be used to add sequentially the successive input signal samples after their weighting. The accumulator is periodically reset after each set of weighted samples has been supplied thereto, which periodic resetting is implemented using a sample counter. Just prior to the resetting of the accumulator, its contents as supplied to a subsequent data latch are latched into that subsequent latch in a subsampling or decimation procedure. Where the filter response is to be used in parallel-bit format, these contents held in the subsequent data latch until the next set of weighted samples have been accumulated. Where the filter response is to be used in serial-bit form, the subsequent data latch can take the form of a parallel-in/serial-out (PISO) shift register with the contents of the accumulator loaded into it in parallel, thereafter to be clocked out serially a bit at a time at some multiple of the loading rate.
In either case the loading procedure requires that the phase of the relatively low sample rate clock used to time loading of the data latch for output signal samples be correctly timed respective to the high sample rate clock supplied to the accumulator to condition it to receive input samples. Loading of the data latch must be completed before the high sample rate clock supplied to the accumulator clocks its reset.
The inventors find that a clocked data latch used for subsampling the decimation filter output signal can be clocked with clocking signals generated by blanking selected pulses in the clocking signals used in preceding portions of the filter. This procedure assures proper temporal alignment of the loading of the clocked data latch.
This arrangement replaces the conventional arrangement where square waves provided from the most significant bit place of the same counter clocked at the high sample rate are used as a basis for generating a set of plural-phase clocking signals at the low sample rate which phases have non-overlapping pulses. In this conventional arrangement the circuitry for eliminating overlap of the high sample rate clocking signal phases and the circuitry for eliminating overlap of the low sample rate clocking signal phases are different circuitry. This causes difficulty in assuming that there is no overlap of the high sample rate pulses used to clock the accumulator and the low sample rate pulses used to clock the succeeding data latch, which difficulty is avoided using the invention
Subsampling time-domain digital filters using accumulators are useful in digital communications for example, in pyramid processing. In pyramid processing a digitized signal is analyzed by subsampling filters into its subspectral components for compression using structural codes; the code is transmitted over a relatively low data rate channel; and the subspectral components are decoded, resampled by interpolation and combined to generate a replica of the original digitized signal.
Subsampling time-domain digital filters are also used in oversampling analog-to-digital converters such as those of the delta-sigma type (sometimes referred to as the sigma-delta type). More particularly, an electronic circuit breaker may use such an oversampling analog-to-digital converter followed by digital comparator circuitry and digital filter circuitry to generate trip signals in the presence of a fault condition. This application is focussed on in this specification, but the teachings of this specification have general application to subsampling filters using accumulators, though used for other purposes.